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1. Field of the Invention
The present invention relates generally to integrated circuit devices used for processing data through communication networks, and more particularly, to methods and apparatuses for processing and managing the flow of data in high speed networks.
2. Description of the Related Art
The Ethernet local area network (LAN) is one of the most popular and widely used computer networks in the world. Since the Ethernet""s beginnings in the early 1970""s, computer networking companies and engineering professionals have continually worked to improve Ethernet product versatility, reliability and transmission speeds. To ensure that new Ethernet products were compatible and reliable, the Institute of Electrical and Electronic Engineers (IEEE) formed a working group to define and promote industry LAN standards. Today, the IEEE has various Ethernet working groups that are responsible for standardizing the development of new Ethernet protocols and products under an internationally well known LAN standard called the xe2x80x9cIEEE 802.3 standard.xe2x80x9d
Currently, there are a wide variety of standard compliant Ethernet products used for receiving, processing and transmitting data over Ethernet networks. By way of example, these networking products are typically integrated into networked computers, network interface cards (NICs), routers, switching hubs, bridges and repeaters. Until recently, common data transmission speeds over Ethernet networks were 10 mega bits per second (Mbps). However, to meet the demand for faster data transmission speeds, the IEEE 802.3 standards committee officially introduced the xe2x80x9cIEEE 802.3u standardxe2x80x9d in May of 1995. This standard is also referred to as the xe2x80x9c100 BASE T Fast Ethernetxe2x80x9d standard because of its ability to perform data transmissions up to about 100 Mbps.
FIG. 1A is a diagrammatic representation of an open systems interconnection (OSI) layered model 10 developed by the International Organization for Standards (ISO) for describing the exchange of information between layers. The OSI layered model 10 is particularly useful for separating the technological functions of each layer, and thereby facilitating the modification or update of a given layer without detrimentally impacting on the functions of neighboring layers. At a lower most layer, the OSI model 10 has a physical layer 12 that is responsible for encoding and decoding data into signals that are transmitted across a particular medium. As is well known in the art, physical layer 12 is also known as the xe2x80x9cPHY layer.xe2x80x9d
Above the physical layer 12, a data link layer 14 is defined for providing reliable transmission of data over a network while performing appropriate interfacing with physical layer 12 and a network layer 16. As shown, data link layer 14 generally includes a logical link layer (LLC) 14a and a media access control layer (MAC) 14b. LLC layer 14a is generally a software function that is responsible for attaching control information to the data being transmitted from network layer 16 to MAC layer 14b. On the other hand, MAC layer 14b is responsible for scheduling, transmitting and receiving data over a link. Thus, MAC layer 14b is primarily responsible for controlling the flow of data over a network, ensuring that transmission errors are detected, and ensuring that transmissions are appropriately synchronized. As is well known in the art, MAC layer 14b generally schedules and controls the access of data to physical layer 12 using a well known carrier sense multiple access with collision detection (CSMA/CD) algorithm.
Network layer 16 is responsible for routing data between nodes in a network, and for initiating, maintaining and terminating a communication link between users connected to the nodes. Transport layer 18 is responsible for performing data transfers within a particular level of service quality. By way of example, a typical software protocol used for performing transport layer 18 functions may be TCP/IP, Novell IPX and NetBeui. Session layer 20 is generally concerned with controlling when users are able to transmit and receive data depending on whether the user""s is capable of full-duplex or half-duplex transmission. Presentation layer 22 is responsible for translating, converting, compressing and decompressing data being transmitted across a medium. As an example, presentation layer 22 functions are typically performed by computer operating systems like Unix, DOS, Microsoft Windows 95, Windows NT and Macintosh OS. Finally, Application layer 24 provides users with suitable interfaces for accessing and connecting to a network.
FIG. 1B is a diagrammatic representation of typical Ethernet packets used for transferring data across a network. A packet generally includes a preamble 30 which is typically 8 bytes long. The last byte (or octet) in the preamble is a start frame delimiter (not shown). After the start frame delimiter octet, a destination address (DA) 32 which is typically 6 bytes is used to identify the node that is to receive the Ethernet packet. Following DA 32, is a source address (SA) 34 which is typically 6 bytes long, SA 34 is used to identify the transmitting node directly on the transmitted packet. After the SA 34, a length/type field (L/T) 36 (typically 2 bytes) is generally used to indicate the length and type of the data field that follows. As is well known in the art, if a length is provided, the packet is classified as an 802.3 packet, and if the type field is provided, the packet is classified as an Ethernet packet.
The following data field is identified as LLC data 38 since the data field also includes information that may have been encoded by the LLC layer 14a. A pad 40 is also shown following LLC data 38. As is well known in the art, if a given Ethernet packet is less than 64 bytes, most media access controllers add a padding of 1""s and 0""s following LLC data 38 in order to increase the Ethernet packet size to at least 64 bytes. Once pad 40 is added, if necessary, a 4 byte cyclic redundancy check (CRC) field is appended to the end of a packet in order to check for corrupted packets at a receiving end. As used herein, a xe2x80x9cframexe2x80x9d should be understood to be a sub-portion of data contained within a packet.
As described above, because MAC layer 14b is responsible for controlling the flow of data over a network, MAC layer 14b is generally responsible for encapsulating received LLC data 38 with an appropriate preamble 30, DA 32, SA 34, DFL 36, Pad 40 and CRC 42. Further, an inter-packet gap (IPG) is shown identifying a time span between transmitted Ethernet packets. Conventionally, the IPG is a fixed value that is defined by the 802.3 standard, and imposed by a suitable MAC layer 14b. For more information on Ethernet network communication technology, reference may be made to issued U.S. Patents entitled Apparatus and Method for Full-Duplex Ethernet Communications having U.S. Pat. Nos. 5,311,114 and 5,504,738. These patents are hereby incorporated by reference.
FIG. 1C is a system architecture representation of a conventional Ethernet media access controller (MAC) 50. As shown, MAC 50 includes a transmit (Tx) MAC controller 54 for processing data received from an upper LLC layer, and a receive (Rx) MAC controller 56 for processing Ethernet packets received from a physical medium 84. From the transmission side, data is typically received from the upper LLC layer through a system bus 78. As shown, all data that is passed to MAC 50 is sent to a bus interface controller 74 through a path 52. In addition, control and command signals are also generally passed in a serial manner to MAC 50 through path 52. Once data is passed into bus interface controller 74, the data is passed into a Tx FIFO 62 which acts as a buffer for holding data received from the upper LLC layer.
In general, both Tx FIFO 62 and a Rx FIFO 64 have associated FIFO control blocks 66 and 68, for passing control information to MAC controller 54, and for triggering the transfer of data stored Tx FIFO 62 and Rx FIFO 68. Therefore, in conventional MAC architectures, once a selected processing control is passed to Tx MAC controller 54 or Rx MAC controller 56, that particular control information will remain as the xe2x80x9cset controlxe2x80x9d for a predetermined number of Ethernet packets. Consequently, the processing operations performed by Tx MAC controller 54 and Rx MAC controller 56 cannot be modified during the transmission of each particular frame (i.e., they may only be modified between transmissions).
Further shown are command status registers 72 and statistics counters 70 that are conventionally used to account for and keep track of processing being performed in Tx MAC controller 54 and Rx MAC controller 56. In this conventional MAC design, path 52 is generally used for passing both data and control signals. However, when information stored in the command status registers 72 and statistics counters 70 is accessed, any data or control signal currently being passed to Tx MAC controller 54 will be halted (which necessarily slows down the network). Accordingly, management tasks that require access to the command status registers 72 and statistics counters 70 will also complete for use of path 52.
Although the conventional MAC architecture 50 has worked well, further improvements to handle increased data throughputs, handle critical flow control issues, and handle management and network diagnostics issues are always desirable. These features are especially desirable as network speeds continue to increase. As an example, in current technology Ethernet networks, flow control tasks are generally not even attempted, and most data transfers are performed as end-to-end dumps over a selected link. That is, once the transmitter parameters are set to perform requested processing (i.e., the packet construction parameters are set), the transmitter will continue dumping packets through the network until the user wants to update the transmitted packet construction parameters. Thus, if an update is requested, the changes to the processing must be passed from the LLC layer down to the MAC layer through the same processing path.
Unfortunately, when both control and data are passed through one processing path, both data and control must compete for bandwidth and only one is processed at one time. Consequently, once a packet transmission or receiving function is initiated, the processing parameters may not be changed. A further disadvantage with prior art Ethernet MAC layer processing is that once an erroneous packet is transmitted, there is generally no way of preventing or aborting its transmission. Therefore, the receive side will necessarily be required to deal with processing more error prone packets.
Furthermore, prior art Ethernet MAC receiving layers are currently unable to efficiently communicate back to the transmitting station in situations where the receiver side of a MAC layer is unable to handle a large queue of packets. As is well known in the art, prior attempts at solving this problem has been to increase the buffer size within the MAC layer. Although increasing buffer sizes may have slowed the problem for current technology 10 Mbps and 100 Mbps Ethernet systems, once transmissions are increased to the gigabit and greater level, increasing buffer sizes will no longer be a reasonable solution in view of the increased data throughput requirements.
It is further pointed out that prior art Ethernet systems are currently unable to provide network managers with an appropriate level of network performance diagnostics abilities. By way of example, when network diagnostics and performance characteristics are performed, network managers typically implement expensive diagnostic and network sniffing equipment that is oftentimes prohibitively expensive when analyzing average size networks. As a result, network managers typically choose to upgrade entire Ethernet systems before attempts are made to trouble shoot a networks performance faults and flow control limitations.
In view of the foregoing, there is a need for methods and apparatuses for media access control (MAC) layer processing that will allow for in-line packet-by packet processing of data information and control information to modify a packet""s characteristics while it is being processed for transmission or reception. In addition, there is a need for methods and apparatuses for a MAC layer processing that allows users to manage the flow of packet data being transmitted and received through a network and accurately perform sophisticated diagnostic testing.
Broadly speaking, the present invention fills these needs by providing methods and apparatuses for a high speed media access controller used to process packet data and control information in an in-line packet-by packet manner. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, a method, or a computer readable medium. Several inventive embodiments of the present invention are described below.
In one embodiment, a media access controller is disclosed. The media access controller includes a transmit media access controller that is configured to process out-going packet data received from an upper layer for transmission to a physical layer. A receive media access controller that is configured to process in-coming packet data received from the physical layer for transmission to the upper layer. A transmit multi-packet queue FIFO for receiving the out-going packet data from the upper layer before being passed to the transmit media access controller. A receive multi-packet queue FIFO for receiving the in-coming packet data that is received by the receive media access controller. The media access controller further including a media access controller manager interfacing with the transmit and receive media access controllers. The media access controller manager being responsible for managing the flow of packet data through the transmit and receive multi-packet queue FIFOs.
In another embodiment, a network interface system for communicating across a network is disclosed. The network interface system includes a media access controller for processing transmit data received an upper layer and transmitting the processed transmit data to a lower layer, and processing receive data received from the lower layer and transmitting the processed receive data to the upper layer. The media access controller being configured to monitor the flow of data between the upper and lower layers. The network interface further including a data bus for communicating data and data control information between the upper layer and the media access controller. A management control bus for communicating management control information between the upper layer and the media access controller, the management control bus being independent of the data bus.
In yet another embodiment, a method for making a media access controller for processing data transmit requests, data receive requests and monitoring data flow through the media access controller is disclosed. The media access controller being configured to communicate with an upper layer and a lower layer. The method includes integrating a first bus for transferring data into and out of the media access controller. Integrating a second bus for communicating management control requests to the media access controller while the transferring of data is in progress. The second bus being coupled to a parallel events processor containing a microprocessor for filtering selected data that is being transferred through the first bus.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.